The present disclosure relates to integrated circuit (IC) cell design and, more particularly, to methods of enhancing power staple insertion.
Computer-aided cell-based design has been developed for quickly designing large scale ICs, such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as standard cells and gate arrays use different types of such building blocks. A standard cell is an integrated circuit that may be implemented with digital logic. An ASIC, such as a system-on-chip (SoC) device, may contain thousands to millions of standard cells. In a standard cell design, each distinct cell in a library may have unique geometries of active, gate, and metal levels. Examples of a standard cell or gate array cell include an inverter, a NAND gate, a NOR gate, a flip-flop, and other similar logic circuits.
During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design. The library includes cells that have been designed for a given IC manufacturing process, such as complementary metal oxide semiconductor (CMOS) fabrication. The cells generally have a fixed height but a variable width, which enables the cells to be placed in rows. Cells typically do not change from one design to the next, but the way in which they are interconnected may, in order to achieve the desired function in a given design. By being able to select the cells from the library for use in the design, the designer can quickly implement a desired functionality without having to custom design the entire integrated circuit from scratch. Thus, the designer will have a certain level of confidence that the integrated circuit will work as intended when manufactured, without having to worry about the details of the individual components that make up each cell.
Cells are normally designed so that routing connections between cells can be made as efficiently as possible. Routing in an IC design is accomplished through routing elements, such as wires in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias are used to connect one metal layer to another. These routing elements perform at least two functions: they connect individual components that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit. For example, clock signals, reset signals, test signals, and power supply voltages may be carried through such routing elements. A well-designed cell layout minimizes congestion in routing global interconnections, which reduces the number of metal layers in or overall size of an integrated circuit layout.
It is useful to construct multi-layer circuits in a way that applied voltages and ground can be accessed as easily as possible. One layer of the multi-layer circuit is the PC (polysilicon) layer, and this layer holds the logic structure in field effect transistor (FET) gates. M0 is the first metal layer that mostly holds the source/drain contacts and the gate contact of the FETs but may also contain interconnections in a horizontal direction. M0 conductors that connect to a source, drain, or gate are often noted as the M0 pin of standard cells. M1 is the second metal layer that is typically reserved for the output pin or a power staple, as well as routing. M2 is the third metal layer that is typically reserved for routing. Other metal layers for power or routing, etc. can be used. Connections between various layers are made by vertical electrical connectors that pass through the wafer called vias where, for example, V0 links M0 to M1, and V1 links M1 to M2.
In order to reduce the size of such structures, sophisticated processes, such as self-aligned double patterning (SADP) can be used, and this can follow a uni-directional design style, wherein M0 and M2 are horizontal and M1 is vertical. That is, in the uni-directional design style, a horizontal M1 conductor is not used, and a power staple stitches the M0 and M2 conductors. The function of the power staple is, therefore, equivalent to the via contacts of other nodes that connect two horizontal conductors.